74LVC1G32GW Nexperia Single 2-input OR gate TSSOP-5

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Garantia:

3 meses direto com a Net Computadores

NCM:

85423190

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novo em embalagem comercial

Garantia:
3 meses direto com a Net Computadores

NCM: 85423190

74LVC1G32GW Nexperia Single 2-input OR gate TSSOP-5

Condição de 74LVC1G32GW: novo em embalagem comercial

Garantia de 74LVC1G32GW: 3 meses direto com a Net Computadores

The 74LVC1G32 is a single 2-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits

Wide supply voltage range from 1.65 V to 5.5 V
Overvoltage tolerant inputs to 5.5 V
High noise immunity
CMOS low power dissipation
IOFF circuitry provides partial Power-down mode operation
±24 mA output drive (VCC = 3.0 V)
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Complies with JEDEC standard:
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to 85 °C and -40 °C to 125 °C.

Maiores detalhes de 74LVC1G32GW no site do fabricante:
https://www.nexperia.com/products/analog-logic-ics/control-logic/gates/or-gates/

Tags de 74LVC1G32GW: 74LVC, 74LVC1G32GW,125, 74LVC1G32GW-125, 74LVC1G32GW 125, 74LVC1G32GW, 74LVC1G32, 74LVC1G32G, VG, V6, ci VG, Ci V6, ci 5 terminais VG, Schmitt-trigger, Schmitt trigger, nexperia

74LVC1G32GW Nexperia Single 2-input OR gate TSSOP-5

Condição de 74LVC1G32GW:
novo em embalagem comercial

Garantia de 74LVC1G32GW:
3 meses direto com a Net Computadores

Wide supply voltage range from 1.65 V to 5.5 V
Overvoltage tolerant inputs to 5.5 V
High noise immunity
CMOS low power dissipation
IOFF circuitry provides partial Power-down mode operation
±24 mA output drive (VCC = 3.0 V)
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Complies with JEDEC standard:
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to 85 °C and -40 °C to 125 °C.